The LDD technique is widely used in high voltage field effect transistor applications to avoid breakdown due to the high electric field intensity at the gate-edge. This technique involves interposing a lightly doped drift region in the drain (LDD region), so as to reduce the electric field intensity to below the breakdown voltage (BV). The length of this LDD region is dependent upon the specific operating range of the transistor. However, in addition to a larger size in the resulting transistor, the drawbacks of an LDD device also include a larger turn-on drain resistance RDS-on), leading to a reduced current drive capability. In power applications, this LDD region needs to be very long, and hence a correspondingly high price is paid for the LDD advantage. In many cases, the RDS-on resistance dominates the total resistance in the device. Hence, the design of a transistor having a lesser on-resistance, but without reducing the breakdown voltage, is extremely valuable.